Project Information     o:\jma\eln_2005\comparateur_vhdl\nybble_comparador.rpt

MAX+plus II Compiler Report File
Version 9.23 3/19/99
Compiled: 11/30/2004 12:46:37

Copyright (C) 1988-1999 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera.  Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner.  Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors.  No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.



***** Project compilation was successful


NYBBLE_COMPARADOR


** DEVICE SUMMARY **

Chip/                     Input Output Bidir  Memory  Memory  			 LCs
POF       Device          Pins  Pins   Pins   Bits % Utilized  LCs  % Utilized

nybble_comparador
      EPF10K20RI240-4      11     3      0    0         0  %    11       0  %

User Pins:                 11     3      0  



Project Information     o:\jma\eln_2005\comparateur_vhdl\nybble_comparador.rpt

** PROJECT COMPILATION MESSAGES **

Info: Design Doctor has given the project a clean bill of health based on the EPLD Rules set


Project Information     o:\jma\eln_2005\comparateur_vhdl\nybble_comparador.rpt

** FILE HIERARCHY **



|comparador:C0|
|comparador:C0|p_nand_2:C01|
|comparador:C0|p_not:C02|
|comparador:C0|p_nand_2:C03|
|comparador:C0|p_nand_2:C04|
|comparador:C0|p_nand_3:C05|
|comparador:C0|p_nand_3:C06|
|comparador:C0|p_not:C07|
|comparador:C0|p_nand_3:C08|
|comparador:C0|p_nand_2:C09|
|comparador:C0|p_nand_2:C10|
|comparador:C0|p_nand_2:C11|
|comparador:C0|p_nand_2:C12|
|comparador:C0|p_nand_3:C13|
|comparador:c|
|comparador:c|p_nand_2:C01|
|comparador:c|p_not:C02|
|comparador:c|p_nand_2:C03|
|comparador:c|p_nand_2:C04|
|comparador:c|p_nand_3:C05|
|comparador:c|p_nand_3:C06|
|comparador:c|p_not:C07|
|comparador:c|p_nand_3:C08|
|comparador:c|p_nand_2:C09|
|comparador:c|p_nand_2:C10|
|comparador:c|p_nand_2:C11|
|comparador:c|p_nand_2:C12|
|comparador:c|p_nand_3:C13|
|comparador:c~117|
|comparador:c~117|p_nand_2:C01|
|comparador:c~117|p_not:C02|
|comparador:c~117|p_nand_2:C03|
|comparador:c~117|p_nand_2:C04|
|comparador:c~117|p_nand_3:C05|
|comparador:c~117|p_nand_3:C06|
|comparador:c~117|p_not:C07|
|comparador:c~117|p_nand_3:C08|
|comparador:c~117|p_nand_2:C09|
|comparador:c~117|p_nand_2:C10|
|comparador:c~117|p_nand_2:C11|
|comparador:c~117|p_nand_2:C12|
|comparador:c~117|p_nand_3:C13|
|comparador:C3|
|comparador:C3|p_nand_2:C01|
|comparador:C3|p_not:C02|
|comparador:C3|p_nand_2:C03|
|comparador:C3|p_nand_2:C04|
|comparador:C3|p_nand_3:C05|
|comparador:C3|p_nand_3:C06|
|comparador:C3|p_not:C07|
|comparador:C3|p_nand_3:C08|
|comparador:C3|p_nand_2:C09|
|comparador:C3|p_nand_2:C10|
|comparador:C3|p_nand_2:C11|
|comparador:C3|p_nand_2:C12|
|comparador:C3|p_nand_3:C13|


Device-Specific Information:o:\jma\eln_2005\comparateur_vhdl\nybble_comparador.rpt
nybble_comparador

***** Logic for device 'nybble_comparador' compiled without errors.




Device: EPF10K20RI240-4

FLEX 10K Configuration Scheme: Passive Serial

Device Options:
    User-Supplied Start-Up Clock               = OFF
    Auto-Restart Configuration on Frame Error  = OFF
    Release Clears Before Tri-States           = OFF
    Enable Chip_Wide Reset                     = OFF
    Enable Chip-Wide Output Enable             = OFF
    Enable INIT_DONE Output                    = OFF
    JTAG User Code                             = 7f

                                                                                                                                         
                                                                                                                                         
                    R R R R R R   R R R R R R R   R R R R R R R   R R R       R R R R   R R R R R R R   R R R R R R R   R R R R R R R R  
                    E E E E E E   E E E E E E E   E E E E E E E   E E E       E E E E   E E E E E E E   E E E E E E E   E E E E E E E E  
                    S S S S S S G S S S S S S S V S S S S S S S G S S S       S S S S V S S S S S S S G S S S S S S S V S S S S S S S S  
                    E E E E E E N E E E E E E E C E E E E E E E N E E E       E E E E C E E E E E E E N E E E E E E E C E E E E E E E E  
                    R R R R R R D R R R R R R R C R R R R R R R D R R R       R R R R C R R R R R R R D R R R R R R R C R R R R R R R R  
                    V V V V V V I V V V V V V V I V V V V V V V I V V V       V V V V I V V V V V V V I V V V V V V V I V V V V V V V V  
                a a E E E E E E N E E E E E E E N E E E E E E E N E E E a b b E E E E N E E E E E E E N E E E E E E E N E E E E E E E E  
                1 2 D D D D D D T D D D D D D D T D D D D D D D T D D D 0 0 3 D D D D T D D D D D D D T D D D D D D D T D D D D D D D D  
              --------------------------------------------------------------------------------------------------------------------------_ 
             / 240 238 236 234 232 230 228 226 224 222 220 218 216 214 212 210 208 206 204 202 200 198 196 194 192 190 188 186 184 182   |_ 
            /    239 237 235 233 231 229 227 225 223 221 219 217 215 213 211 209 207 205 203 201 199 197 195 193 191 189 187 185 183 181    | 
      #TCK |  1                                                                                                                         180 | ^DATA0 
^CONF_DONE |  2                                                                                                                         179 | ^DCLK 
     ^nCEO |  3                                                                                                                         178 | ^nCE 
      #TDO |  4                                                                                                                         177 | #TDI 
    VCCINT |  5                                                                                                                         176 | GNDINT 
        pt |  6                                                                                                                         175 | RESERVED 
        gr |  7                                                                                                                         174 | RESERVED 
        eg |  8                                                                                                                         173 | RESERVED 
      eg_b |  9                                                                                                                         172 | RESERVED 
    GNDINT | 10                                                                                                                         171 | RESERVED 
      gr_b | 11                                                                                                                         170 | VCCINT 
      pt_b | 12                                                                                                                         169 | RESERVED 
  RESERVED | 13                                                                                                                         168 | RESERVED 
  RESERVED | 14                                                                                                                         167 | RESERVED 
  RESERVED | 15                                                                                                                         166 | RESERVED 
    VCCINT | 16                                                                                                                         165 | GNDINT 
  RESERVED | 17                                                                                                                         164 | RESERVED 
  RESERVED | 18                                                                                                                         163 | RESERVED 
  RESERVED | 19                                                                                                                         162 | RESERVED 
  RESERVED | 20                                                                                                                         161 | RESERVED 
  RESERVED | 21                                                                                                                         160 | VCCINT 
    GNDINT | 22                                                                                                                         159 | RESERVED 
  RESERVED | 23                                                                                                                         158 | RESERVED 
  RESERVED | 24                                                                                                                         157 | RESERVED 
  RESERVED | 25                                                                                                                         156 | RESERVED 
  RESERVED | 26                                                                                                                         155 | GNDINT 
    VCCINT | 27                                                                                                                         154 | RESERVED 
  RESERVED | 28                                                                                                                         153 | RESERVED 
  RESERVED | 29                                                                                                                         152 | RESERVED 
  RESERVED | 30                                                                                                                         151 | RESERVED 
  RESERVED | 31                                                     EPF10K20RI240-4                                                     150 | VCCINT 
    GNDINT | 32                                                                                                                         149 | RESERVED 
  RESERVED | 33                                                                                                                         148 | RESERVED 
  RESERVED | 34                                                                                                                         147 | RESERVED 
  RESERVED | 35                                                                                                                         146 | RESERVED 
  RESERVED | 36                                                                                                                         145 | GNDINT 
    VCCINT | 37                                                                                                                         144 | RESERVED 
  RESERVED | 38                                                                                                                         143 | RESERVED 
  RESERVED | 39                                                                                                                         142 | RESERVED 
  RESERVED | 40                                                                                                                         141 | RESERVED 
  RESERVED | 41                                                                                                                         140 | VCCINT 
    GNDINT | 42                                                                                                                         139 | RESERVED 
  RESERVED | 43                                                                                                                         138 | RESERVED 
  RESERVED | 44                                                                                                                         137 | RESERVED 
  RESERVED | 45                                                                                                                         136 | RESERVED 
  RESERVED | 46                                                                                                                         135 | GNDINT 
    VCCINT | 47                                                                                                                         134 | RESERVED 
  RESERVED | 48                                                                                                                         133 | RESERVED 
  RESERVED | 49                                                                                                                         132 | RESERVED 
  RESERVED | 50                                                                                                                         131 | RESERVED 
  RESERVED | 51                                                                                                                         130 | VCCINT 
    GNDINT | 52                                                                                                                         129 | RESERVED 
  RESERVED | 53                                                                                                                         128 | RESERVED 
  RESERVED | 54                                                                                                                         127 | RESERVED 
  RESERVED | 55                                                                                                                         126 | RESERVED 
  RESERVED | 56                                                                                                                         125 | GNDINT 
    VCCINT | 57                                                                                                                         124 | ^MSEL0 
      #TMS | 58                                                                                                                         123 | ^MSEL1 
     #TRST | 59                                                                                                                         122 | VCCINT 
  ^nSTATUS | 60                                                                                                                         121 | ^nCONFIG 
           |      62  64  66  68  70  72  74  76  78  80  82  84  86  88  90  92  94  96  98 100 102 104 106 108 110 112 114 116 118 120  _| 
            \   61  63  65  67  69  71  73  75  77  79  81  83  85  87  89  91  93  95  97  99 101 103 105 107 109 111 113 115 117 119   | 
             \--------------------------------------------------------------------------------------------------------------------------- 
                R R R R R R R R G R R R R R R R V R R R R R R R G R R R V b a b G R R V R R R R R R R G R R R R R R R V R R R R R R R R  
                E E E E E E E E N E E E E E E E C E E E E E E E N E E E C 2 3 1 N E E C E E E E E E E N E E E E E E E C E E E E E E E E  
                S S S S S S S S D S S S S S S S C S S S S S S S D S S S C       D S S C S S S S S S S D S S S S S S S C S S S S S S S S  
                E E E E E E E E I E E E E E E E I E E E E E E E I E E E I       I E E I E E E E E E E I E E E E E E E I E E E E E E E E  
                R R R R R R R R N R R R R R R R N R R R R R R R N R R R N       N R R N R R R R R R R N R R R R R R R N R R R R R R R R  
                V V V V V V V V T V V V V V V V T V V V V V V V T V V V T       T V V T V V V V V V V T V V V V V V V T V V V V V V V V  
                E E E E E E E E   E E E E E E E   E E E E E E E   E E E           E E   E E E E E E E   E E E E E E E   E E E E E E E E  
                D D D D D D D D   D D D D D D D   D D D D D D D   D D D           D D   D D D D D D D   D D D D D D D   D D D D D D D D  
                                                                                                                                         
                                                                                                                                         


N.C. = No Connect, This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).
GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
GNDIO = Dedicated ground pin, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.

^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin. 
@ = Special-purpose pin. 
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration.  JTAG pin stability prevents accidental loading of JTAG instructions.


Device-Specific Information:o:\jma\eln_2005\comparateur_vhdl\nybble_comparador.rpt
nybble_comparador

** RESOURCE USAGE **

Logic                Column       Row                                   
Array                Interconnect Interconnect         Clears/     External  
Block   Logic Cells  Driven       Driven       Clocks  Presets   Interconnect
A13      7/ 8( 87%)   0/ 8(  0%)   2/ 8( 25%)    0/2    0/2      10/22( 45%)   
A14      4/ 8( 50%)   0/ 8(  0%)   1/ 8( 12%)    0/2    0/2       9/22( 40%)   


Embedded             Column       Row                                   
Array     Embedded   Interconnect Interconnect         Read/      External  
Block     Cells      Driven       Driven       Clocks  Write    Interconnect


Total dedicated input pins used:                 6/6      (100%)
Total I/O pins used:                             8/183    (  4%)
Total logic cells used:                         11/1152   (  0%)
Total embedded cells used:                       0/48     (  0%)
Total EABs used:                                 0/6      (  0%)
Average fan-in:                                 3.18/4    ( 79%)
Total fan-in:                                  35/4608    (  0%)

Total input pins required:                      11
Total input I/O cell registers required:         0
Total output pins required:                      3
Total output I/O cell registers required:        0
Total buried I/O cell registers required:        0
Total bidirectional pins required:               0
Total reserved pins required                     0
Total logic cells required:                     11
Total flipflops required:                        0
Total packed registers required:                 0
Total logic cells in carry chains:               0
Total number of carry chains:                    0
Total logic cells in cascade chains:             0
Total number of cascade chains:                  0
Total single-pin Clock Enables required:         0
Total single-pin Output Enables required:        0

Synthesized logic cells:                         3/1152   (  0%)

Logic Cell and Embedded Cell Counts

Column:  01  02  03  04  05  06  07  08  09  10  11  12  EA  13  14  15  16  17  18  19  20  21  22  23  24  Total(LC/EC)
 A:      0   0   0   0   0   0   0   0   0   0   0   0   0   7   4   0   0   0   0   0   0   0   0   0   0     11/0  
 B:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 C:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 D:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 E:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  
 F:      0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0   0      0/0  

Total:   0   0   0   0   0   0   0   0   0   0   0   0   0   7   4   0   0   0   0   0   0   0   0   0   0     11/0  



Device-Specific Information:o:\jma\eln_2005\comparateur_vhdl\nybble_comparador.rpt
nybble_comparador

** INPUTS **

                                                    Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
 212      -     -    -    --      INPUT                0    0    0    3  a0
 240      -     -    A    --      INPUT                0    0    0    3  a1
 239      -     -    A    --      INPUT                0    0    0    3  a2
  91      -     -    -    --      INPUT                0    0    0    3  a3
 211      -     -    -    --      INPUT                0    0    0    3  b0
  92      -     -    -    --      INPUT                0    0    0    3  b1
  90      -     -    -    --      INPUT                0    0    0    3  b2
 210      -     -    -    --      INPUT                0    0    0    3  b3
   8      -     -    A    --      INPUT                0    0    0    1  eg
   7      -     -    A    --      INPUT                0    0    0    1  gr
   6      -     -    A    --      INPUT                0    0    0    1  pt


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:o:\jma\eln_2005\comparateur_vhdl\nybble_comparador.rpt
nybble_comparador

** OUTPUTS **

       Fed By Fed By                                Fan-In    Fan-Out
 Pin     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   9      -     -    A    --     OUTPUT                0    1    0    0  eg_b
  11      -     -    A    --     OUTPUT                0    1    0    0  gr_b
  12      -     -    A    --     OUTPUT                0    1    0    0  pt_b


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable


Device-Specific Information:o:\jma\eln_2005\comparateur_vhdl\nybble_comparador.rpt
nybble_comparador

** BURIED LOGIC **

                                                    Fan-In    Fan-Out
 IOC     LC     EC   Row  Col  Primitive    Code      INP  FBK  OUT  FBK  Name
   -      2     -    A    13        OR2    s           3    0    0    1  |COMPARADOR:c|P_NAND_3:C05|~8~1
   -      3     -    A    13        OR2        !       2    1    0    1  |COMPARADOR:c|P_NAND_3:C05|:8
   -      1     -    A    14        OR2        !       2    1    0    1  |COMPARADOR:c|P_NAND_3:C13|:8
   -      2     -    A    14        OR2        !       3    0    0    1  |COMPARADOR:C0|P_NAND_3:C13|:8
   -      4     -    A    13        OR2    s           4    0    0    1  |COMPARADOR:C3|P_NAND_2:C09|~5~1
   -      1     -    A    13        OR2    s           4    0    0    1  |COMPARADOR:C3|P_NAND_2:C09|~5~2
   -      6     -    A    13       AND2        !       1    2    1    0  |COMPARADOR:C3|P_NAND_2:C09|:5
   -      7     -    A    13        OR2        !       2    1    1    0  |COMPARADOR:C3|P_NAND_3:C05|:8
   -      7     -    A    14        OR2        !       2    1    1    0  |COMPARADOR:C3|P_NAND_3:C13|:8
   -      5     -    A    13        OR2        !       2    1    0    1  |COMPARADOR:c~117|P_NAND_3:C05|:8
   -      3     -    A    14        OR2        !       2    1    0    1  |COMPARADOR:c~117|P_NAND_3:C13|:8


Code:

s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register


Device-Specific Information:o:\jma\eln_2005\comparateur_vhdl\nybble_comparador.rpt
nybble_comparador

** FASTTRACK INTERCONNECT UTILIZATION **

Row FastTrack Interconnect:

          Global         Left Half-      Right Half-
         FastTrack       FastTrack       FastTrack 
Row     Interconnect    Interconnect    Interconnect    Input Pins     Output Pins     Bidir Pins
A:       5/ 96(  5%)     0/ 48(  0%)     3/ 48(  6%)    5/16( 31%)      3/16( 18%)     0/16(  0%)
B:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
C:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
D:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
E:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)
F:       0/ 96(  0%)     0/ 48(  0%)     0/ 48(  0%)    0/16(  0%)      0/16(  0%)     0/16(  0%)


Column FastTrack Interconnect:

         FastTrack                                 
Column  Interconnect    Input Pins     Output Pins     Bidir Pins
01:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
02:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
03:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
04:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
05:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
06:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
07:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
08:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
09:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
10:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
11:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
12:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
13:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
14:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
15:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
16:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
17:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
18:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
19:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
20:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
21:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
22:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
23:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
24:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)
EA:      0/24(  0%)     0/4(  0%)      0/4(  0%)       0/4(  0%)


Device-Specific Information:o:\jma\eln_2005\comparateur_vhdl\nybble_comparador.rpt
nybble_comparador

** EQUATIONS **

a0       : INPUT;
a1       : INPUT;
a2       : INPUT;
a3       : INPUT;
b0       : INPUT;
b1       : INPUT;
b2       : INPUT;
b3       : INPUT;
eg       : INPUT;
gr       : INPUT;
pt       : INPUT;

-- Node name is 'eg_b' 
-- Equation name is 'eg_b', type is output 
eg_b     = !_LC6_A13;

-- Node name is 'gr_b' 
-- Equation name is 'gr_b', type is output 
gr_b     = !_LC7_A13;

-- Node name is 'pt_b' 
-- Equation name is 'pt_b', type is output 
pt_b     = !_LC7_A14;

-- Node name is '|COMPARADOR:c|P_NAND_3:C05|~8~1' 
-- Equation name is '_LC2_A13', type is buried 
-- synthesized logic cell 
_LC2_A13 = LCELL( _EQ001);
  _EQ001 =  a0 &  gr
         # !b0 &  gr
         #  a0 & !b0;

-- Node name is '|COMPARADOR:c|P_NAND_3:C05|:8' 
-- Equation name is '_LC3_A13', type is buried 
!_LC3_A13 = _LC3_A13~NOT;
_LC3_A13~NOT = LCELL( _EQ002);
  _EQ002 =  a1 &  _LC2_A13
         # !b1 &  _LC2_A13
         #  a1 & !b1;

-- Node name is '|COMPARADOR:c|P_NAND_3:C13|:8' 
-- Equation name is '_LC1_A14', type is buried 
!_LC1_A14 = _LC1_A14~NOT;
_LC1_A14~NOT = LCELL( _EQ003);
  _EQ003 = !a1 &  b1
         # !a1 & !_LC2_A14
         #  b1 & !_LC2_A14;

-- Node name is '|COMPARADOR:C0|P_NAND_3:C13|:8' 
-- Equation name is '_LC2_A14', type is buried 
!_LC2_A14 = _LC2_A14~NOT;
_LC2_A14~NOT = LCELL( _EQ004);
  _EQ004 = !a0 &  b0
         # !a0 &  pt
         #  b0 &  pt;

-- Node name is '|COMPARADOR:C3|P_NAND_2:C09|~5~1' 
-- Equation name is '_LC4_A13', type is buried 
-- synthesized logic cell 
_LC4_A13 = LCELL( _EQ005);
  _EQ005 = !a0 & !a1 & !b0 & !b1
         #  a0 & !a1 &  b0 & !b1
         # !a0 &  a1 & !b0 &  b1
         #  a0 &  a1 &  b0 &  b1;

-- Node name is '|COMPARADOR:C3|P_NAND_2:C09|~5~2' 
-- Equation name is '_LC1_A13', type is buried 
-- synthesized logic cell 
_LC1_A13 = LCELL( _EQ006);
  _EQ006 = !a2 & !a3 & !b2 & !b3
         # !a2 &  a3 & !b2 &  b3
         #  a2 & !a3 &  b2 & !b3
         #  a2 &  a3 &  b2 &  b3;

-- Node name is '|COMPARADOR:C3|P_NAND_2:C09|:5' 
-- Equation name is '_LC6_A13', type is buried 
!_LC6_A13 = _LC6_A13~NOT;
_LC6_A13~NOT = LCELL( _EQ007);
  _EQ007 =  eg &  _LC1_A13 &  _LC4_A13;

-- Node name is '|COMPARADOR:C3|P_NAND_3:C05|:8' 
-- Equation name is '_LC7_A13', type is buried 
!_LC7_A13 = _LC7_A13~NOT;
_LC7_A13~NOT = LCELL( _EQ008);
  _EQ008 =  a3 & !_LC5_A13
         # !b3 & !_LC5_A13
         #  a3 & !b3;

-- Node name is '|COMPARADOR:C3|P_NAND_3:C13|:8' 
-- Equation name is '_LC7_A14', type is buried 
!_LC7_A14 = _LC7_A14~NOT;
_LC7_A14~NOT = LCELL( _EQ009);
  _EQ009 = !a3 & !_LC3_A14
         #  b3 & !_LC3_A14
         # !a3 &  b3;

-- Node name is '|COMPARADOR:c~117|P_NAND_3:C05|:8' 
-- Equation name is '_LC5_A13', type is buried 
!_LC5_A13 = _LC5_A13~NOT;
_LC5_A13~NOT = LCELL( _EQ010);
  _EQ010 =  a2 & !_LC3_A13
         # !b2 & !_LC3_A13
         #  a2 & !b2;

-- Node name is '|COMPARADOR:c~117|P_NAND_3:C13|:8' 
-- Equation name is '_LC3_A14', type is buried 
!_LC3_A14 = _LC3_A14~NOT;
_LC3_A14~NOT = LCELL( _EQ011);
  _EQ011 = !a2 & !_LC1_A14
         #  b2 & !_LC1_A14
         # !a2 &  b2;



Project Information     o:\jma\eln_2005\comparateur_vhdl\nybble_comparador.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = on
   Rules                                  = EPLD Rules


Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = on

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:05
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   Design Doctor                          00:00:00
   --------------------------             --------
   Total Time                             00:00:08


Memory Allocated
-----------------

Peak memory allocated during compilation  = 11,450K
